{"version":"1.0","provider_name":"Electronics Maker","provider_url":"https:\/\/electronicsmaker.com","author_name":"Electronics Maker","author_url":"https:\/\/electronicsmaker.com\/author\/electronics","title":"Smart High Level Synthesis (HLS) Tool Suite Enables C++ Based Algorithm Development Using Microchip\u2019s PolarFire\u00ae FPGA Platform - Electronics Maker","type":"rich","width":600,"height":338,"html":"<blockquote class=\"wp-embedded-content\" data-secret=\"b6Xr480stU\"><a href=\"https:\/\/electronicsmaker.com\/smart-high-level-synthesis-hls-tool-suite-enables-c-based-algorithm-development-using-microchips-polarfire-fpga-platform\">Smart High Level Synthesis (HLS) Tool Suite Enables C++ Based Algorithm Development Using Microchip\u2019s PolarFire\u00ae FPGA Platform<\/a><\/blockquote><iframe sandbox=\"allow-scripts\" security=\"restricted\" src=\"https:\/\/electronicsmaker.com\/smart-high-level-synthesis-hls-tool-suite-enables-c-based-algorithm-development-using-microchips-polarfire-fpga-platform\/embed#?secret=b6Xr480stU\" width=\"600\" height=\"338\" title=\"&#8220;Smart High Level Synthesis (HLS) Tool Suite Enables C++ Based Algorithm Development Using Microchip\u2019s PolarFire\u00ae FPGA Platform&#8221; &#8212; Electronics Maker\" data-secret=\"b6Xr480stU\" frameborder=\"0\" marginwidth=\"0\" marginheight=\"0\" scrolling=\"no\" class=\"wp-embedded-content\"><\/iframe><script type=\"text\/javascript\">\n\/* <![CDATA[ *\/\n\/*! This file is auto-generated *\/\n!function(d,l){\"use strict\";l.querySelector&&d.addEventListener&&\"undefined\"!=typeof URL&&(d.wp=d.wp||{},d.wp.receiveEmbedMessage||(d.wp.receiveEmbedMessage=function(e){var t=e.data;if((t||t.secret||t.message||t.value)&&!\/[^a-zA-Z0-9]\/.test(t.secret)){for(var s,r,n,a=l.querySelectorAll('iframe[data-secret=\"'+t.secret+'\"]'),o=l.querySelectorAll('blockquote[data-secret=\"'+t.secret+'\"]'),c=new RegExp(\"^https?:$\",\"i\"),i=0;i<o.length;i++)o[i].style.display=\"none\";for(i=0;i<a.length;i++)s=a[i],e.source===s.contentWindow&&(s.removeAttribute(\"style\"),\"height\"===t.message?(1e3<(r=parseInt(t.value,10))?r=1e3:~~r<200&&(r=200),s.height=r):\"link\"===t.message&&(r=new URL(s.getAttribute(\"src\")),n=new URL(t.value),c.test(n.protocol))&&n.host===r.host&&l.activeElement===s&&(d.top.location.href=t.value))}},d.addEventListener(\"message\",d.wp.receiveEmbedMessage,!1),l.addEventListener(\"DOMContentLoaded\",function(){for(var e,t,s=l.querySelectorAll(\"iframe.wp-embedded-content\"),r=0;r<s.length;r++)(t=(e=s[r]).getAttribute(\"data-secret\"))||(t=Math.random().toString(36).substring(2,12),e.src+=\"#?secret=\"+t,e.setAttribute(\"data-secret\",t)),e.contentWindow.postMessage({message:\"ready\",secret:t},\"*\")},!1)))}(window,document);\n\/* ]]> *\/\n<\/script>\n","thumbnail_url":"https:\/\/electronicsmaker.com\/wp-content\/uploads\/2021\/09\/Microchip-PolarFire-FPGA.jpg","thumbnail_width":600,"thumbnail_height":333,"description":"Enhances accessibility to PolarFire FPGAs for hardware acceleration in edge compute systems Mumbai, Sept. 3, 2021 \u2014 The need to combine performance with low power consumption in edge compute applications has driven demand for Field Programmable Gate Arrays (FPGAs) to be used as power-efficient accelerators while also providing flexibility and speeding time to market. However, [&hellip;]"}